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Choosing SPI NAND Flash: How It Differs from SPI NOR, with GigaDevice GD5F1GQ5 / GD5F2GQ5
GigaDeviceSPI NANDSPI NORGD5F1GQ5GD5F2GQ5FlashECC

Choosing SPI NAND Flash: How It Differs from SPI NOR, with GigaDevice GD5F1GQ5 / GD5F2GQ5

SPI NAND reads by page, erases by block and needs ECC and bad-block management — in exchange for far higher density and lower cost-per-bit than SPI NOR. Using GD5F1GQ5 (1Gb) and GD5F2GQ5 (2Gb), learn when to move from NOR to NAND and how to second-source.

JL Reviewed by JLink Technology engineering team · Updated 2026-06-24

SPI NAND vs SPI NOR: the architectural difference

SPI NOR is byte-addressable and can execute code in place (XIP), with low read latency and essentially no factory bad blocks — but its cost-per-bit is high and density is limited. SPI NAND reads and writes by page and erases by block, cannot do XIP, but has a much lower cost-per-bit and scales to gigabit densities. The trade-off is that NAND cells inherently produce bit errors and may ship with — and accumulate — bad blocks, so they need ECC and bad-block management (BBM), using the spare/OOB area to hold check bytes and bad-block markers. Modern SPI NAND (including GigaDevice GD5F) puts the ECC engine on-chip (on-die ECC) to simplify host software.

GD5F1GQ5 / GD5F2GQ5 specs, and what “ECC-free” means

Both GD5F1GQ5 (1Gb) and GD5F2GQ5 (2Gb) use a 2KB main page plus 128B spare and 64 pages per block (a 128KB block), with 1024 blocks on the GD5F1GQ5 and 2048 on the GD5F2GQ5; the interface supports x1/x2/x4 (Standard/Dual/Quad SPI) and DTR, up to 104MHz, in −40~85°C and −40~105°C grades, WSON8 package, JEDEC manufacturer ID 0xC8. One label to clarify: the datasheet’s “ECC-free” does not mean “no ECC” — it means the chip already has on-die ECC, so the host needs no external ECC; check bytes are generated into the spare area automatically on write and corrected on read. Another selection trap is voltage: the GD5F series comes in 1.8V (RE suffix) and 3.3V (UE suffix) variants, with both 1Gb and 2Gb available in each, so pair parts by the same voltage variant when laying out a board.

When to move from NOR to NAND

There is no single hard threshold, but the rule of thumb is: once you need roughly 256Mb–1Gb or more and that data does not need to execute in place (XIP), SPI NAND’s density and cost-per-bit advantages start to win clearly; 1–2Gb is exactly where SPI NOR struggles and SPI NAND takes over. Boot code that must execute directly still belongs in SPI NOR, or you can use on-SoC SRAM/DRAM to code-shadow — load the NAND contents and run from RAM. A common split in small Linux/IoT systems is bootloader in SPI NOR, kernel and file system in SPI NAND, using a file system such as UBI/UBIFS that provides wear leveling and bad-block management.

Second-sourcing and selection notes

GD5F can often match other SPI NAND at the pin and package level (also WSON8, the same SPI/Dual/Quad command family), but it is not an unconditional drop-in: GigaDevice (ID 0xC8), Winbond W25N (0xEF) and Micron MT29F (0x2C) differ in JEDEC ID, spare-area size, on-die ECC strength and Read-ID return format, so changing the die means re-validating the driver’s ID table, ECC-status handling and bad-block logic — you cannot swap on footprint alone. 1–2Gbit SPI NAND suits IoT data logging, large read-mostly assets such as voice/image/AI models, the rootfs of a small Linux system, and OTA dual-image schemes; when interfacing an existing 1.8V or 3.3V platform, remember to pick the correct RE/UE voltage variant.

Products mentioned

GD5F1GQ5 In Stock

GD5F1GQ5 1Gbit SPI NAND Flash

The GD5F1GQ5 is a 1Gbit SPI NAND Flash from GigaDevice with a 2KB page and 128KB block (64 pages), supporting x1/x2/x4 (Quad) SPI. The series splits into on-chip-ECC variants (UE, 2.7~3.6V, up to 133MHz) and ECC-free variants (RE, 1.7~2.0V, 104MHz), in WSON8 — for code and data storage on MCUs/SoCs.

SPI NANDFlash1Gbit
GD5F2GQ5 In Stock

GD5F2GQ5 2Gbit SPI NAND Flash

The GD5F2GQ5 is a 2Gbit serial SPI NAND Flash from GigaDevice with an x1/x2/x4 (Quad) SPI interface up to 104MHz, 2.7~3.6V supply, a 2KB+128B page, on-die hardware ECC, in a WSON8 (8×6mm) package. At twice the density of the cataloged GD5F1GQ5 (1Gbit), it suits MCU/SoC code and data storage, IoT, set-top boxes, and industrial/automotive (−40~+105°C) use.

SPI NAND Flash2GbitQuad SPI
GD25Q128 In Stock

GD25Q128 128Mbit SPI NOR Flash

The GD25Q128 is a 128Mbit (16MB) serial SPI NOR Flash, 2.7~3.6V supply, up to 133MHz, with Dual/Quad I/O, 4KB sector and 32/64KB block erase, and 256-byte page program. In SOP8 / WSON8 with a standard JEDEC pinout and command set, it is a common second source for the Winbond W25Q128.

SPI NOR Flash128MbitQuad SPI

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