What Is Hardwired TCP/IP? How WIZnet W5500 / W6100 / W6300 Offload Your MCU
Hardwired TCP/IP puts the whole protocol stack in silicon — the MCU just reads and writes socket registers over SPI/QSPI. Compare W5500 (IPv4), W6100 (IPv4/IPv6 dual stack) and W6300 (IPv6 + QSPI throughput) to pick the right part.
What is hardwired TCP/IP?
A typical networked MCU runs a software TCP/IP stack (lwIP, uIP) in firmware, so the CPU processes TCP, UDP, IPv4, ICMP and ARP — consuming significant Flash, RAM and cycles, often alongside an RTOS. Hardwired TCP/IP instead implements the entire stack in the chip’s silicon: WIZnet integrates the TCP/IP stack, the 10/100 Ethernet MAC and the PHY into a single chip, so the MCU simply reads and writes socket registers inside the chip over SPI/QSPI and the chip does the protocol work — offloading networking from the MCU to dedicated hardware.
What does offloading the MCU buy you?
The MCU no longer runs a software stack, saving Flash/RAM and CPU cycles and removing the need to bring in an RTOS just for networking; packet buffering lives in the chip’s on-chip memory (32KB on the W5500/W6100), not in MCU RAM. In development you just add a simple socket program to get online, which keeps porting and validation simple. Because the stack is fixed in hardware and separated from your application, behaviour is stable and predictable — useful for industrial links that must stay up (stability and isolation are design-level advantages; real-world results still depend on the system).
W5500 / W6100 / W6300 compared
The W5500 supports hardwired IPv4 (TCP, UDP, ICMP, IGMP, ARP, PPPoE), 8 independent sockets, a 32KB internal TX/RX buffer and SPI (rated up to 80MHz in the datasheet); the product page lists ~55Mbps throughput, in a 48-LQFP with 3.3V and 5V-tolerant I/O. The W6100 adds an IPv4/IPv6 dual stack with the same 8 sockets and 32KB buffer, a host interface of SPI plus an 8-bit parallel bus, and SOCKET-less commands for IPv6 auto-configuration; note that the official datasheet lists the W6100 as “W5100S pin-to-pin compatible” and does not claim W5500 pin compatibility, so it is not a drop-in on an existing W5500 board. The W6300 is also IPv4/IPv6 dual-stack but uses Quad SPI (Single/Dual/Quad modes) for higher throughput and a larger 64KB buffer total (TX 32KB + RX 32KB, allocatable 0–32KB per socket); the product page lists 90Mbps-and-above throughput, in 48-LQFP / 48-QFN.
How to choose, and where it fits
Need IPv4 only, lowest cost, a proven part → W5500. Need an IPv4/IPv6 dual stack, an SPI or parallel host, and ~10/100 throughput → W6100. Need IPv6 and higher throughput, with a QSPI host, to push toward 100Mbps → W6300. All three provide 8 independent hardware sockets for multiple simultaneous connections. These hardwired TCP/IP chips suit resource-constrained MCUs and links that must stay up: industrial IoT and Industry 4.0 endpoints, serial-to-Ethernet gateways, PLCs and factory-automation controllers, remote monitoring and data acquisition (SCADA, telemetry), building automation and networked sensors.
Products mentioned
W5500 Hardwired TCP/IP Ethernet Controller
W5500 is WIZnet's flagship Ethernet controller with a unique hardwired TCP/IP stack, enabling direct network connectivity without software TCP/IP implementation. Connects to the host MCU via SPI, features 32KB TX/RX buffer, supports up to 8 sockets — the most widely adopted Ethernet chip in the Arduino/Raspberry Pi ecosystem.
W6100 IPv4/IPv6 Dual-Stack Hardwired TCP/IP Controller
The W6100 is an advanced successor to the W5500, distinguished by supporting both IPv4 and IPv6 dual stacks entirely in hardware. It integrates a 10/100 MAC and PHY with 8 hardware sockets and is pin-compatible with the W5100S — an ideal choice when devices must migrate to IPv6.
W6300 IPv4/IPv6 Hardwired TCP/IP Ethernet Controller
The W6300 is WIZnet's first Ethernet controller with a dual IPv4/IPv6 hardwired TCP/IP stack, using a high-speed QSPI (single/dual/quad) host interface, a system clock up to 150MHz, and throughput up to ~90Mbps. With an embedded 10/100 PHY (auto-negotiation, Auto-MDIX), 8 hardware sockets, a 64KB buffer, and ICMPv6/WOL support, in 48-LQFP/QFN at 3.3V with 5V-tolerant I/O, it suits IPv6-ready industrial and IoT devices.
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