Ethernet PHY Selection: RMII vs MII, and What to Watch When Replacing LAN8720A with DAVICOM DM9162
How do you choose between RMII and MII? The key is the clock. DM9162 and LAN8720A are both RMII 10/100 PHYs sharing the clause-22 MDIO interface, so they are functional second sources — but packages, straps and firmware PHY-init differ, making it an alternative that needs a layout and firmware review, not a blind drop-in.
RMII vs MII: the difference, and how to choose
MII runs on 4-bit data with two 25MHz clocks (TX/RX) supplied by the PHY, needing about 16–18 signal lines; RMII switches to 2-bit data and a single shared 50MHz reference clock, needing only about 7–9 lines — half the pins. The first selection question is: does your MAC provide or accept a 50MHz REF_CLK? If so, choose RMII — fewer pins and easier routing, the mainstream choice on modern STM32/GD32/ESP32-class MCUs; if the MAC only offers MII or a 50MHz reference is inconvenient, use MII. The RMII 50MHz can be supplied by an external oscillator, generated by the PHY from a 25MHz crystal and output, or output by the MAC — always confirm the clock direction is consistent.
DM9161A / DM9162 / LAN8720A compared
DAVICOM’s DM9161A and DM9162 are both 10/100 PHYs, both selectable MII or RMII, both with auto-negotiation and Auto-MDIX, both clause-22 MDC/MDIO managed and on a single 3.3V supply; the DM9162 is the industrial-temperature part with more packages (LQFP-48, QFN-32 and more). Microchip’s LAN8720A is an RMII-only 10/100 PHY in a fixed 24-pin QFN (4×4mm, smallest footprint), strap-selectable between “external 50MHz supplied” and “generate 50MHz internally from a 25MHz crystal and output it,” also clause-22 managed and 3.3V (with an internal 1.2V regulator and variable I/O voltage). All three are compatible at the “standard RMII + MDIO” layer; they differ in interface flexibility (the DAVICOM parts offer both modes, the LAN8720A is RMII-only), package and temperature grade.
DM9162 “replacing” LAN8720A: a second source, not a blind drop-in
Because both are RMII 10/100 PHYs using the IEEE 802.3 clause-22 MDIO management interface, the interface looks compatible to the MAC, so the DM9162 can serve as a functional second source for the LAN8720A (reducing supply risk). But their packages differ (the DM9162’s QFN does not share the LAN8720A’s 24-pin QFN pinout), strap-pin definitions differ, and vendor-specific registers (16 and up) differ — so this is an alternative that “needs a new PCB footprint and a firmware PHY-init review,” and you cannot claim a pin-to-pin direct replacement. To adopt it, redo the footprint, verify the straps and PHY address, and check the parts of the driver that touch vendor registers.
What firmware changes when you swap PHY, plus selection criteria
The good news: the standard registers are identical on every clause-22 PHY — register 0 (BMCR: reset, speed, duplex, auto-negotiation, power-down) and register 1 (BMSR: link status, capabilities), plus auto-negotiation registers 4–6, are all portable. What changes is only the PHY address, any init that writes vendor registers 16 and up, and the strap/clock-mode settings — never copy one PHY’s vendor-register writes onto another. Selection criteria: first the clock (does the MAC supply/accept 50MHz) decides MII/RMII; for industrial temperature choose the right part number (DM9162, LAN8720Ai); package and board area (smallest is the LAN8720A 24-pin, while DAVICOM suits MII flexibility or reusing an existing footprint); and finally include multi-source availability — use the standardized RMII+MDIO interface to lower the risk of going end-of-life.
Products mentioned
DM9162 10/100M Ethernet PHY Transceiver
The DM9162 is a DAVICOM 10/100Mbps single-port Fast Ethernet PHY transceiver compliant with IEEE 802.3/802.3u, offering an MII/RMII MAC interface, HP Auto-MDIX, and auto-negotiation. A single 3.3V supply with 5V-tolerant I/O in a 48-pin LQFP / 32-pin QFN — commonly paired with MCUs/SoCs that expose an MII/RMII MAC.
DM9161A Single-Port 10/100M Ethernet PHY
DM9161A is a DAVICOM single-port 10/100M Fast Ethernet PHY that connects to a MAC via MII/RMII interface, supporting Auto-Negotiation and MDI/MDI-X. Suitable for designs requiring a discrete MAC/PHY architecture — commonly paired with FPGA or SoC integrated MACs.
Need these components or design help?
JLink Technology provides parts, datasheets, and engineering support.
Request a Quote